EECS 391 - VLSI Systems Design
CATALOG DESCRIPTION: Design of CMOS digital integrated circuits, concentrating on architectural and topological issues. Tradeoffs in custom design, standard cells, gate arrays. Use of VLSI design tools on a small project.
REQUIRED TEXTS: "CMOS Digital Integrated Circuits Analysis & Design" by Sung-Mo (Steve) Kang and Yusuf Leblebici; 3rd edition
COURSE COORDINATOR/INSTRUCTOR: Ilya Mikhelson
COURSE GOALS: Students will become familiar with the realities of CMOS VLSI design: Proper layout structures, and the impact of fabrication technologies; Methods for optimizing the area, speed, and power of circuit layouts; The use of CAD tools for both schematic and layout of complex CMOS circuits; Methods for testing of circuit designs, both during creation and on individual die; Tradeoffs in device implementation technologies, such as Full-custom, standard cell, gate array, FPGA, PLD.
PREREQUISITES: EECS 203
DETAILED COURSE TOPICS:
- CMOS Introduction.
- CMOS Fabrication.
- Layout in Cadence.
- Inverters (static and dynamic properties).
- Combinational Logic.
- Sequential Logic.
- Dynamic Logic.
- Memory Circuits.
- ·Arithmetic Blocks.
COMPUTER USAGE: Students will require the use of the Cadence Virtuoso toolsuite for most assignments, as well as the final project.
- Basic layout and schematic capture techniques in Cadence Virtuoso.
- Advanced layout and simulation in Cadence Virtuoso.
- The design of a small-scale CMOS circuit from scratch (ALU, Systolic circuit, etc.)
- Homework – 20%
- Labs – 15%
- Final Project – 35%
- Midterm Exam – 20%
- Final Exam – 10%
COURSE OBJECTIVES: When a student completes this course, s/he should be able to:
- Analyze digital circuits for speed and power.
- Create CMOS layouts of various gates.
- Understand design rules.
- Understand the tradeoffs of VLSI design.
- Understand the sources of resistance and capacitance in circuits and be able to account for them in designs.
- Optimize the speed and area of a CMOS circuit.
- Understand various technologies and the tradeoffs therein.