EECS 391 - VLSI Systems Design
CATALOG DESCRIPTION: Design of CMOS digital integrated circuits, concentrating on architectural and topological issues. Tradeoffs in custom design, standard cells, gate arrays. Use of VLSI design tools on a small project.
REQUIRED TEXTS: "CMOS Digital Integrated Circuits Analysis & Design" by Sung-Mo (Steve) Kang and Yusuf Leblebici; 3rd edition
COURSE INSTRUCTOR: Ilya Mikhelson
COURSE COORDINATOR: Joseph Friedman
COURSE GOALS: Students will become familiar with the realities of CMOS VLSI design: Proper layout structures, and the impact of fabrication technologies; Methods for optimizing the area, speed, and power of circuit layouts; The use of CAD tools for both schematic and layout of complex CMOS circuits; Methods for testing of circuit designs, both during creation and on individual die; Tradeoffs in device implementation technologies, such as Full-custom, standard cell, gate array, FPGA, PLD.
PREREQUISITES : EECS 303
PREREQUISITES BY TOPIC:
1 .Fundamentals of logic design, including Boolean Algebra, Karnaugh Maps, and schematics (gate-level circuits).
2. The use of Mentor Graphics CAD tools for schematic capture, simulation.
4. Binary unsigned and 2's complement arithmetic.
DETAILED COURSE TOPICS
• Introduction to transistors and CMOS circuits.
• CMOS fabrication technology and design rules.
• Sticks diagrams and CMOS layout.
• Registers and clocking methodologies.
• Resistance, capacitance, and performance optimization.
• Logical Effort.
• Dynamic logic, Pseudo-nMOS, and other logic families.
• Arithmetic circuits: Adders, Multipliers, ALUs.
• Datapath structures and memories.
• Chip implementation styles: Full custom, standard cells, MPGA, FPGA, PLD.
• Testing of CMOS circuitry.
COMPUTER USAGE: Students will require the use of the Mentor Graphics toolsuite for most assignments, as well as the final project.
• Basic layout and schematic capture techniques in Mentor Graphics
• Advanced layout and simulation in Mentor Graphics
• The design of a small-scale CMOS circuit from scratch (ALU, Systolic circuit, etc.)
Homework and Lab assignments - 20 %
Midterm exam - 20 %
Final exam - 20 %
Final Project - 40 %
COURSE OBJECTIVES: When a student completes this course, s/he should be able to:
• Create CMOS layouts of simple and complex gates.
• Understand design rules and their impact on structured design.
• Understand resistance and capacitance, and use this information to optimize designs.
• Design a clocking structure and methodology for CMOS circuitry.
• Optimize the speed and area of a CMOS circuit.
• Understand the tradeoffs in dynamic logic structures, and create appropriate circuits in these design styles.
• Create efficient datapath and arithmetic circuits that work well in transistor-level designs.
• Understand the architecture of memory structures.
• Understand the strengths and weaknesses of current implementation technologies, and create designs appropriate for each technology.
• Create a testing methodology for an ASIC design.
• Use Mentor Graphics CAD toolsuite to create and test moderately complex circuit layouts.
ABET CONTENT CATEGORY: 100% Engineering (Design component).