CATALOG DESCRIPTION: The course discusses modern processor architectures, the constraints that limit their design and programmability, and promising techniques to mitigate these constraints.

REQUIRED TEXTS: None; we'll draw material from seminal and recent publications in top conferences.

COURSE COORDINATOR: Nikos Hardavellas

COURSE OBJECTIVES: The course aims to offer a firm background for research in computer architecture. The students that successfully complete the course will be exposed to a variety of cutting-edge research topics, be able to read and critique research publications in computer architecture, perform conference-quality paper reviews, perform research presentations, write research reports, and gain familiarity with state-of-the-art tools for research in computer architecture. Along with providing technical
knowledge, the course also aims to develop the student's ethos as researchers and research referees, and sharpen the students team-participation skills.

PREREQUISITES: EECS 361 or instructor's consent. EECS 358, EECS 452, and EECS 453 are useful but not required.

DETAILED COURSE TOPICS: The course will have a seminar format. The students will present papers in the class, write paper reviews, and discuss each paper in depth during class meetings. The class will cover recent research in various topics:

* Memory and caches (e.g., NUCA caches, prefetching and streaming, 3D-die stacking, phase-change memory)
* On-chip interconnects
* Programmability (e.g., transactional memory, enforcing sequential consistency)
* Speculative threading and parallelization
* Debugging/monitoring support
* Power/thermal management
* Reliability and fault tolerance
* Process variability
* Unconventional/specialized architectures

GRADES: class participation 20%, presentation 20%, homework assignments 20%, project 40%. There are no final exams.