ECE 361 - Computer Architecture
Fall 2004

Instructor:	Alok Choudhary	choudhar(AT)ece.northwestern.edu
		Office Hours: by Appointment
TAs:	Avery Ching	aching(AT)ece.northwestern.edu
		Office Hours: Wed. 2-3 @ L460
	Kenin Coloma	kcoloma(AT)ece.northwestern.edu
		Office Hours: Thurs 1-3 @ L460
Class Info:	TTh 11:00-12:20	Tech. M128

Textbook: D. Patterson and J. Hennessy, Computer Organization and Design: The Hardware/Software Interface
Midterm 11/16

11/01/04	Just uploaded the correct new tutorial. This is the tutorial we had you do several weeks ago.
10/28/04	A quick word of warning that you may have already heard: unless you really know exactly what you're doing, do not move any of your Mentor Graphics files around from the Unix shell. The Mentor Graphics tools may get very confused.
10/28/04	Posted final project which is due 12/2/04.
10/22/04	Posted a new version of homework two which should clear up some confusion surrounding the figures in problem 2. Namely, the bottom figure is the ALU slice for the most significant bit, and the upper figure represents all other ALU slices.
10/19/04	Posted Homework 2 and Lab 1 (ALU)
10/19/04	Posted fully corrected Homework 1.
10/12/04	Correction on Homework 1. In problem 6, the table lists the execution time for program 2 on computer A as 100 but it should be a 1000.
10/7/04	Homework 1 has been posted.
10/5/04	The new Tutorial is up
10/4/04	I've added a FAQ and a brief setup guide for Mentor Graphics. Check it out under Resources. The Tutorial for tomorrow will be posted shortly.
9/24/04	Sorry, I've re-uploaded the lectures, they were a little outdated
9/24/04	Added 3rd Edition readings.
9/23/04	Welcome to Computer Architecture! Website's up! Enjoy.

Topic	2nd Edition	3rd Edition
Introduction and Metrics	Chapters 1 and 2	Chapters 1 and 4
Instruction Set Architecture	Chapter 3 sections 3.1-3.11, 3.13, 3.14	Chapter 2 sections 2.1-2.10, 2.13, 2.15, 2.17, 2.18
Arithmetic	Chapter 4 sections 4.1-4.8	Chapter 3 sections 3.1-3.6
Datapath & Control	Chapter 5 sections 5.1-5.4	Chapter 5 sections 5.1-5.5
Pipelining	Chapter 6 sections 6.1-6.6	Chapter 6 sections 6.1-6.6
Caching	Chapter 7 sections 7.1-7.5	Chapter 7 sections 7.1-7.5