Time squeezing for tiny devices. Yuanbo Fan, Simone Campanoni, Russ Joseph. Proceedings of the 46th International Symposium on Computer Architecture (ISCA) 2019

An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor. Tianyu Jia, Russ Joseph, Jie Gu. IEEE Journal of Solid-State Circuits 54 (8), 2327-23382019

An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution. Tianyu Jia, Russ Joseph, Jie Gu. IEEE International Solid-State Circuits Conference-(ISSCC) 2019

Cocoa: synergistic cache compression and error correction in capacity sensitive last level caches. Chao Yan, Russ Joseph. Proceedings of the International Symposium on Memory Systems (MEMSYS) 2017

An instruction driven adaptive clock phase scaling with timing encoding and online instruction calibration for a low power microprocessor. Tianyu Jia, Russ Joseph, Jie Gu. IEEE 44th European Solid State Circuits Conference (ESSCIRC) 2018

Compiler-guided instruction-level clock scheduling for timing speculative processors. Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph. 55th ACM/ESDA/IEEE Design Automation Conference (DAC 2018)

Software-guided greybox design methodology with integrated power and clock management. Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu. IEEE 60th International Midwest Symposium on Circuits and Systems 2017

Greybox design methodology: A program driven hardware co-optimization with ultra-dynamic clock management. T Jia, Y Fan, R Joseph, J Gu. 54th ACM/EDAC/IEEE Design Automation Conference (DAC) 2017

D2M: data-driven model for fast and accurate timing error simulation in statically scheduled microprocessors. Yuanbo Fan, Russ Joseph Summer Computer Simulation Conference 2017

Enabling Deep Voltage Scaling in Delay Sensitive L1 Caches. C Yan, R Joseph. IEEE/IFIP Dependable Systems and Networks (DSN), 2016.

Exploration of associative power management with instruction governed operation for ultra-low power design. T Jia, Y Fan, R Joseph, J Gu. Proceedings of the 53rd Annual Design Automation Conference, 2016.

Embedded system and application aware design of deregulated energy delivery systems X He, RP Dick, R Joseph 2015 Compilers, Architecture and Synthesis for Embedded Systems (CASES)

Spatially-and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging X He, RP Dick, R Joseph Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, 2012

Hardware Virtual-machine-based emulation of future generation high-performance computing systems PG Bridges, D Arnold, KT Pedretti, M Suresh, F Lu, P Dinda, R Joseph The International Journal of High Performance Computing Applications.

Reliability modeling and management of nanophotonic on-chip networks Z Li, M Mohamed, X Chen, E Dudley, K Meng, L Shang, AR Mickelson, R Joseph, M Vachharajani, Bchwartz,Y Sun IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Identifying and predicting timing-critical instructions to boost timing speculation J Xin, R Joseph Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

Efficient parameter variation sampling for architecture simulations F Lu, R Joseph, G Trajcevski, S Liu 2011 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Exploring circuit timing-aware language and compilation G Hoang, RB Findler, R Joseph 2011 ACM International Conference on Architectural Support for Programming Languages and Operating Systems.

A case for alternative nested paging models for virtualized systems G Hoang, C Bae, J Lange, L Zhang, P Dinda, R Joseph IEEE Computer Architecture Letters.

Process variation characterization of chip-level multiprocessors L Zhang, LS Bai, RP Dick, L Shang, R Joseph Proceedings of the 46th Annual Design Automation Conference.

Exploiting locality to improve circuit-level timing speculation J Xin, R Joseph IEEE Computer Architecture Letters.

Multi-optimization power management for chip multiprocessors K Meng, R Joseph, RP Dick, L Shang Proceedings of the 17th international conference on Parallel architectures.

Three-dimensional chip-multiprocessor run-time thermal management C Zhu, Z Gu, L Shang, RP Dick, R Joseph IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Runtime thermal management of three-dimensional chip multiprocessors C Zhu, Z Gu, L Shang, RP Dick, R Joseph Proceedings Workshop on Quality-Aware Design.

Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems S Kim, RP Dick, R Joseph 2007 Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Power, thermal, and reliability modeling in nanometer-scale microprocessors D Brooks, RP Dick, R Joseph, L Shang IEEEE Micro 27.

Modeling and characterizing power variability in multicore architectures K Meng, F Huebbers, R Joseph, Y Ismail IEEE International Symposium on Performance Analysis of Systems & Software, 2007.

Understanding voltage variations in chip multiprocessors using a distributed power-delivery network MS Gupta, JL Oatley, R Joseph, GY Wei, DM Brooks Design, Automation & Test in Europe Conference & Exhibition, 2007.

Process variation aware cache leakage management K Meng, R Joseph International Symposium on Low Power Electronics and Design, 2006.

Physical resource matching under power asymmetry K Meng, F Huebbers, R Joseph, Y Ismail P=ac2 Conference, IBM TJ Watson Research Center, Yorktown, NY, 2006

Exploring salvage techniques for multi-core architectures R Joseph Workshop on High Performance Computing Reliability Issues (HPCRI-2005)

Wavelet analysis for microprocessor design: Experiences with wavelet-based di/dt characterization R Joseph, Z Hu, M Martonosi IEEE International Symposium on High-Performance Computer Architecture, 2004. HPCA-10

Spectral analysis for characterizing program power and performance R Joseph, M Martonosi, Z Hu IEEE International Symposium on Performance Analysis of Systems & Software, 2004.

Control techniques to eliminate voltage emergencies in high performance processors IEEE International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 R Joseph, D Brooks, M Martonosi

Run-time power estimation in high performance microprocessors R Joseph, M Martonosi International Symposium on Low Power Electronics and Design, 2001.

Live, runtime power measurements as a foundation for evaluating power/performance tradeoffs R Joseph, D Brooks, M Martonosi Workshop on Complexity Effectice Design WCED, held in conjunction with ISCA-28, 2001.