Yan Pan (Pan Yan) at Niagara Falls, Toronto, May 2008
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Research Interests  I have a wide range of research interests from system level design to low level circuit performance modeling. Some of the recent topics include:
  • Architectural Techniques for Mitigating Process Variation
    • Process variation modeling/mitigation in the 3D Integration era
    • Process variation modeling/mitigation for cache structures
  • Interconnect Networks for Chip Multi-Processors
    • Efficient hierarchical network topology design for many-core CMPs
    • Adopting emerging signaling technologies for Network-on-Chip
    • Network-on-Chip evaluation methodologies, evaluation framework.
  • Empathic Computer Architectures
    • Human-aware /Satisfaction-directed low-power techniques
  • Design Automation for Neuroscience Simulation Platform
    • Simulator for Early Stages in Rat Whisker Neural Circuits

While I enjoy the variety of perspectives from these projects, I am trying to focus on two of these topics that interest me most:

(1) On-Chip network evaluation methodology / Traffic Characterization

trafficThe prospect of many-core CMPs calls for research in high-performance on-chip communication fabrics. In this process, adopting accurate evaluation methodolgy is fundamentally important . However, traditional evaluation methodologies are inherently limited by either humongous simulation time or drastically simplified assumptions. By carefully studying the nature of on-chip traffic load/pattern, I aim to construct an accurate yet efficient evaluation framework that scales well with the booming of core count on a chip.

(2) Impact of process variation in 3D integration era.

3d integrationProcess variation has been a hot topic around for some time. However, the introduction of 3D integration yields new challenges and opportunities. Novel architectural techniques are needed to mitigate the impact of process variation while taking into account the new complications like pre-stacking testing, heat dissipation, etc. Thorough evaluation will be critical to the establishment of any proposed technique.

   
Projects  
Hierarchical Topology   On-chip Network / Evaluation Project

The prospect of many-core CMPs calls for research in high-performance on-chip communication fabrics. In this process, adopting accurate evaluation methodolgy is fundamentally important . However, traditional evaluation methodologies are inherently limited by either humongous simulation time or drastically simplified assumptions. By carefully studying the nature of on-chip traffic load/pattern, I aim to construct an accurate yet efficient evaluation framework that scales well with the booming of core count on a chip.
3D Cache Spliting   Process Variation Modeling / Mitigation Project

Process variation has been a hot topic around for some time. However, the introduction of 3D integration yields new challenges and opportunities. Novel architectural techniques are needed to mitigate the impact of process variation while taking into account the new complications like pre-stacking testing, heat dissipation, etc. Thorough evaluation will be critical to the establishment of any proposed technique.
Sensors for User Feedback   Empathic Systems Project

In this project, we investigate the potential of expoiting user variance for system optimization. Realizing that the ultimate goal of system optimization, in many cases, is to satisfy the end user, we try to benefit from feedback directly obtained from the users.

We demonstrated, in a case study, that biometric information, such as Galvanic Skin Resistance (GSR), pupil dialation and key pressure levels can be utilized to predict the user satisfaction of a computer system. With such information, we can build significantly more efficient computer systems that inteligently saves power without annoying the current user.

This work was nominated for Best Paper Award in MICRO '08. [pdf]
Mouse Whisker  Rat Whisker Neural Simulation Project

This is a inter-disciplinary project where we computer engineers try to provide a feasible high-performance simulation platform for neural scientists to verify various neuroscientific hypotheses. Current efforts include:
  • FPGA supported early neural circuit simulator for rat whisker system.
    • Preliminary results presented in FPL'08. [pdf]
  • Spiking neuron circuit simulator in C++. (In progress)
    • Probablistically firing and multi-dimentional first stage neuron modeling.
    • Summation based 2nd stage neuron modeling for curvature prediction.
    
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Last Updated on October 20, 2009

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